A high voltage IC for use in driving an inverter, or the like is disclosed in, for example, U.S. Pat. No. 5,736,774 or Proc. of ISPSD 2004, p. 385, H. Akiyama, et al. Mitsubishi Electric Co., Ltd.
FIG. 31 shows a schematic sectional view of a prior-art high voltage IC 90 which employs an SOI substrate and trench separation.
In the high voltage IC 90 shown in FIG. 31, a low potential (GND) reference circuit, a high potential (floating) reference circuit and a level shift circuit are respectively provided in the SOI layer 1a of an SOI substrate 1 having a buried oxide film 3. Besides, respective regions for forming the GND reference circuit, floating reference circuit and level shift circuit are insulatingly (dielectrically) separated by the buried oxide film 3 of the SOI substrate 1 and the sidewall oxide films 4s of trenches 4. Incidentally, the buried oxide film 3 is underlaid with a thick support substrate 2 made of silicon (Si), and the SOI substrate 1 is formed by the sticking of the substrates.
In the level shift circuit of the high voltage IC 90, a circuit element of high breakdown voltage is required for joining the low potential reference circuit and the high potential reference circuit. A lateral MOS transistor (LDMOS) 9 in the level-shift-circuit forming region shown in FIG. 31 adopts a so-called “SOI-RESURF structure” in order to ensure a breakdown voltage.
A high voltage in the level shift circuit is applied to the drain D of the LDMOS 9 as shown in the figure. In the LDMOS 9 in FIG. 31, the breakdown voltage in the lateral direction of a section is ensured by the SOI-RESURF structure, which is formed by a surface p-type impurity layer and the buried oxide film 3. Besides, regarding a breakdown voltage in the vertical direction of the section, a high voltage applied between the drain D and a ground (GND) is divided by the SOI layer 1a of low concentration and the buried oxide film 3, thereby to moderate an electric field in the SOI layer 1a. 
In the semiconductor device wherein an insulatingly separated LDMOS like the LDMOS 9 in FIG. 31 is formed in the SOI layer on the buried oxide film, the impurity concentration and thickness of the SOI layer and the thickness of the buried oxide film need to be optimally designed for the purpose of ensuring the breakdown voltage in the vertical direction of the section.
However, when a high breakdown voltage of or above 1000 V is to be attained by this method, a buried oxide film thicker than 5 μm and an SOI layer thicker than 50 μm are required. On the other hand, the achievable upper-limit thickness of the buried oxide film is about 5 μm in the present situation, in relation to the warp of the SOI substrate, etc. Besides, the thickness of the SOI layer is usually on the order of several μm to 20 μm, and when the SOI layer is thickened, a trench working load increases. With the LDMOS 9 in the level-shift-circuit forming region in FIG. 31, therefore, it is a limitation to ensure a breakdown voltage of about 600 V, and a breakdown voltage of 1200 V as is required in a 400V power source system, an EV automobile, etc. cannot be ensured.
In order to solve the above problem, another semiconductor device 10 to be described below has been proposed as a related art.
FIG. 32 is a fundamental equivalent circuit diagram of the semiconductor device 10.
In the semiconductor device 10 shown in FIG. 32, n (n≧2) transistor elements Tr1-Trn which are insulatingly separated from one another are successively connected in series between a ground (GND) potential and a predetermined potential Vs, with a first stage being the side of the GND potential and with the nth stage being the side of the predetermined potential Vs. The gate terminal of the transistor element Tr1 of the first stage serves as the input terminal of the semiconductor device 10. The output of the semiconductor device 10 is derived from the terminal on the side of the predetermined potential Vs in the transistor element Trn of the nth stage, and through a load resistor (not shown) having a predetermined resistance. Incidentally, an output signal is derived in a state where a reference potential has been converted (level-shifted) from the GND potential of an input signal to the predetermined potential Vs, whereby the output signal has been inverted relative to the input signal.
In the operation of the semiconductor device 10 in FIG. 32, the voltage between the GND potential and the predetermined potential Vs is divided by the n transistor elements Tr1-Trn, and the respective transistor elements Tr1-Trn of the first to nth stages bear corresponding voltage ranges. Accordingly, a breakdown voltage required of each of the transistor elements Tr1-Trn becomes substantially one nth as compared with a breakdown voltage in the case where the voltage between the GND potential and the predetermined potential Vs is borne by a single transistor element. Accordingly, even transistor elements which can be inexpensively manufactured by employing a general manufacturing method and each of which has an ordinary breakdown voltage can form a semiconductor device which ensures a high breakdown voltage required as a whole, by appropriately setting the number n of the transistor elements in the semiconductor device 10 in FIG. 32. By the way, in the semiconductor device 10 in FIG. 32, the n transistor elements Tr1-Trn should preferably have the same breakdown voltages. Thus, the voltages (breakdown voltages) which the respective transistor elements Tr1-Trn inserted between the GND potential and the predetermined potential bear can be equalized and minimized.
Concretely, by way of example, a MOS transistor element having a breakdown voltage of about 150 V can be easily formed by the general manufacturing method, by employing an SOI substrate that includes a buried oxide film having a thickness of about 2 μm. Accordingly, a semiconductor device of high breakdown voltage can be realized in such a way that the n transistor elements Tr1-Trn which are insulatingly separated from one another by insulating separation trenches are formed on the SOI substrate, so as to constitute the semiconductor device 10 which consists of the transistor elements of the n stages connected in series. By way of example, the transistor elements each having the breakdown voltage of 150 V are connected in series in two stages, four stages and eight stages as shown in FIG. 32, whereby semiconductor devices 10 having breakdown voltages of 300V, 600V and 1200V can be formed, respectively. Accordingly, a wafer structure (the thicknesses of an SOI layer and the buried oxide film, the impurity concentration of the SOI layer, etc.) need not be altered in accordance with the breakdown voltages. Besides, the working depths of the insulating separation trenches are constant, and even a required breakdown voltage of or above 1000 V can be easily incarnated.
In the above way, the semiconductor device 10 shown in FIG. 32 can ensure any required breakdown voltage, and it can be inexpensively manufactured by employing the general manufacturing method for semiconductor devices.
FIG. 33 is a diagram showing in detail a level shift circuit portion and a floating-reference-gate drive circuit portion in a high voltage IC 100, and it is a diagram showing the arrangement of the respective circuit elements of the semiconductor device 10 applied to the level shift circuit and shown in the fundamental equivalent circuit diagram of FIG. 32. FIG. 34 is a sectional view taken along line XXXIV-XXXIV in FIG. 33, and it is a view showing the structures of the respective transistor elements.
As shown in the sectional view of FIG. 34, in the high voltage IC 100, then transistor elements Tr1-Trn in the semiconductor device 10 in FIG. 32 as is applied to the level shift circuit are formed in the N conductive type SOI layer 1a of an SOI structure semiconductor substrate 1 having a buried oxide film 3. Incidentally, the buried oxide film 3 is underlaid with a thick support substrate 2 made of silicon (Si), and the SOI substrate 1 is formed by the sticking of the substrates.
The n transistor elements Tr1-Trn are LDMOS (Lateral Double-diffused MOS) transistor elements, and they are insulatingly separated from one another by insulating separation trenches 4 which reach the buried oxide film 3.
As shown in FIG. 33, in the semiconductor device 10 of the high voltage IC 100, n-ply (n-fold) insulating separation trenches T1-Tn are formed, and the n transistor elements Tr1-Trn insulatingly separated from one another are successively arranged one by one in respective field regions surrounded with the n-ply insulating separation trenches T1-Trn, in such a manner that the transistor elements of the respective stages are included in the corresponding field regions. Thus, voltages which are applied to the respective field regions surrounded with the n-ply insulating separation trenches are equalized in accordance with voltage increases from the GND potential to the predetermined potential, and the voltage ranges to be borne by then transistor elements Tr1-Trn can be shifted in due order from the GND potential toward the predetermined potential. Incidentally, only one of the n-ply insulating separation trenches T1-Tn exists between the respectively adjacent transistor elements. Therefore, the connection wiring operations of the n transistor elements Tr1-Trn are facilitated, and the semiconductor device 10 can be made small in size by reducing an occupation area.
As stated above, in the semiconductor device 10, the n transistor elements Tr1-Trn may be the transistor elements each having the ordinary breakdown voltage. Thus, the high voltage IC 100 shown in FIG. 33 can ensure a breakdown voltage of 1200V, and it is a high voltage IC suitable for driving the inverter of an on-vehicle motor or for driving the inverter of an on-vehicle air conditioner. Incidentally, the above proposed techniques have already been applied for Japanese Patent Applications No. 2004-308724, No. 2005-121306 and No. 2005-227058.
Meanwhile, characteristics in the case where a dV/dt surge entered in applying the semiconductor device 10 shown in FIG. 32, to the level shift circuit portion of the high voltage IC 100, were simulated. As a result, it has been revealed that a problem to be stated below is existent.
FIG. 35 is a diagram showing the configuration of a semiconductor device 11 into which the semiconductor device 10 shown in FIG. 33 has been simplified. FIG. 36 is an equivalent circuit diagram of the semiconductor device 11 as was employed in the simulation. FIG. 37 is a diagram showing simulation results, namely, the changes-with-time of potentials at the individual points of the semiconductor device 11 attributed to the surge input.
An SOI substrate having a buried oxide film is employed for the semiconductor device 11 shown in FIG. 35, and six lateral MOS transistors (LDMOSS) 11t are formed in an SOI layer on the buried oxide film. Each LDMOS 11t has a pattern in which a drain D, a gate G and a source S are concentrically arranged as shown in the figure. Besides, each LDMOS 11t is surrounded with a first insulating separation trench Z1 which reaches the buried oxide film and which is indicated by a circle of thick solid line in the figure, thereby to be insulatingly separated from the environs.
In the semiconductor device 11 in FIG. 35, second insulating separation trenches Z2 which similarly reach the buried oxide film and which are indicated by squares of thick solid lines in the figure are formed in multiple fashion. The LDMOSs 11t insulatingly separated by the first insulating separation trenches Z1 are respectively arranged one by one in corresponding field regions F1-F6 surrounded with the multiple second insulating separation trenches Z2. Incidentally, a field region Fh which lies inside the field region F6 is a region where a high voltage (HV) circuit, a power source pad, an output pad, etc. are formed, and a field region Fg which lies outside the field region F1 is a region where a ground (GND) pad, an input pad, etc. are formed.
In the semiconductor device 11 in FIG. 35, the six LDMOSs 11t are successively connected in series between a ground (GND) potential and a predetermined power source potential, with a first stage of GND potential side being the outer peripheral side of the sextuple second insulating separation trenches Z2 and with a sixth stage of power source potential side being the inner peripheral side thereof. Incidentally, sign Rin denotes an input resistor, and sign Rout denotes an output resistor. In the semiconductor device 11, a gate terminal in the first-stage LDMOS lit is used as an input terminal. Besides, the output resistor Rout is connected between the sixth-stage LDMOS 11t and the power source pad, and an output is derived from between the terminal of the sixth-stage LDMOS 11t on the power source potential side thereof and the output resistor Rout. In the semiconductor device 11, combinations each of which consists of a resistance element R and a capacitance element C that are connected in parallel are connected in series in multiple stages, thereby to divide the voltage between the GND potential and the power source potential, and the gates of the LDMOSs 11t of the second stage are respectively connected to the branch points of the series connection.
As shown in an equivalent circuit in FIG. 36, in the simulation of the semiconductor device 11 at the application of the dV/dt surge, the equivalent circuit is constituted by gate connection lines each consisting of the resistance element R and the capacitance element C, the source-drain lines of the LDMOSs 11t, SOI layer lines and support substrate lines, in consideration of parasitic capacitances, etc. which develop in the SOI substrate.
FIG. 37 shows the simulation results of the semiconductor device 11 in the case where the dV/dt surge of 100 kV/μsec entered. In FIG. 37, there are shown the change-with-time graphs of potentials at the output pad, the drains Ds of the LDMOSs 11t of the respective stages, and the power source side of the input resistor Rin. The change-with-time of the output pad potential is the same as the change-with-time of the input dV/dt surge. By the way, in FIG. 37, the drains Ds of the fifth and sixth stages have an identical potential, and no voltage is applied across the LDMOS 11t of the sixth stage. This is ascribable to the circuit arrangement shown in FIG. 36, and is not an essential problem.
In the semiconductor device 11 in a steady state, as stated before, the power source voltage can be equally divided by the six transistor elements 11t. In contrast, as shown in FIG. 37, in the case where the dV/dt surge of 100 kV/μsec entered, a large potential difference develops between the output pad and the drain D of the LDMOS 11t of the sixth stage. That is, a large voltage is applied across the output resistor Rout, and the output resistor Rout will break down.